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A primer on memory consistency and cache coherence Daniel J. Sorin, Mark D. Hill, David A. Wood.
Author
Sorin, Daniel J.
Published
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, c2011.
Call Number
QA76.9.M45 S676 2011eb,005.43 22
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Computer architecture performance evaluation methods Lieven Eeckhout.
Author
Eeckhout, Lieven.
Published
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, c2010.
Call Number
QA76.9.A73 E322 2010,004.22 22
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Hardware and software support for virtualization / Edouard Bugnion, Jason Nieh, Dan Tsafrir.
Author
Bugnion, Edouard,
Call Number
QA76.9.V5 B844 2017,005.43 23
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Multi-core cache hierarchies Rajeev Balasubramonian, Norman Jouppi, Naveen Muralimanohar.
Author
Balasubramonian, Rajeev.
Published
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, c2011.
Call Number
TK7895.M4 B255 2011,621.39732 22
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Quantum computing for computer architects Tzvetan S. Metodi, Arvin I. Faruque, Frederic T. Chong.
Author
Metodi, Tzvetan S.
Published
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, c2011.
Call Number
QA76.889 .M476 2011,004.1 22
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Transactional memory Tim Harris, James Larus, Ravi Rajwar.
Author
Harris, Tim,
Published
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, c2010.
Call Number
QA76.545 .H277 2010,005.758 22
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