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Introduction to logic synthesis using Verilog HDL / Robert B. Reese, Mitchell A. Thornton
Author
Reese, Robert B.
Published
[San Rafael, CA] : Morgan & Claypool, c2006.
Call Number
TK7868.L6 R4i
Location
ห้องสมุดสำนักการเรียนรู้ตลอดชีวิตฯ

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Introduction to logic synthesis using Verilog HDL Robert B. Reese, Mitchell A. Thornton.
Author
Reese, Robert B.
Published
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2006.
Call Number
TK7868.L6 R445 2006,621.395 22,MoCl 6812806 IEEE

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