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Finite state machine datapath design, optimization, and implementation Justin Davis, Robert Reese.

Author

Davis, Justin S.,

Published

San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2008.

Call Number

TK7888.3 .D284 2008,621.3916 22,MoCl 6812910 IEEE

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Introduction to logic synthesis using Verilog HDL / Robert B. Reese, Mitchell A. Thornton

Author

Reese, Robert B.

Published

[San Rafael, CA] : Morgan & Claypool, c2006.

Call Number

TK7868.L6 R4i

Location

ห้องสมุดสำนักการเรียนรู้ตลอดชีวิตฯ

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Introduction to logic synthesis using Verilog HDL Robert B. Reese, Mitchell A. Thornton.

Author

Reese, Robert B.

Published

San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2006.

Call Number

TK7868.L6 R445 2006,621.395 22,MoCl 6812806 IEEE

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Found: 3 Titles

Finite state machine datapath design, optimization, and implementation Justin Davis, Robert Reese.

Introduction to logic synthesis using Verilog HDL / Robert B. Reese, Mitchell A. Thornton

Introduction to logic synthesis using Verilog HDL Robert B. Reese, Mitchell A. Thornton.

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